VHDL koda, to je pravo?

[lzh08]

library IEEE;
uporabu ieee.std_logic_1164.all;

SUBJEKTA MCU IS
LUKA
(
nDataStrobe: U Std_Logic;
nAddrStrobe: U Std_Logic;
nWri: U Std_Logic;
nReset: U Std_Logic;
Podaci: InOut Std_Logic_Vector (7 DOWNTO 0);
nWait: OUT Std_Logic;
Nack: OUT Std_Logic;
);
END MCU;

ARHITEKTURA Akcija MCU JE
TIP stanje je (st0, ST1, ST2, ST3, ST4, ST5);
SIGNAL Cur_State, Next_State: Država: = st0;
SIGNAL RegDataTemp: std_logic_vector (7 downto 0);
SIGNAL RegAddrTemp: std_logic_vector (7 downto 0);

BEGIN

DataWrite: PROCES (Cur_State, nDataStrobe, nWri)
BEGIN
SLUČAJ Cur_State IS
KADA st0 => nWait <= '0 ';
if (nWri = '1 ') onda
Next_State <= st0;
drugo
Next_State <= ST1;
end if;
KADA ST1 => RegDataTemp <= podataka;
if (nDataStrobe = '1 ') onda
Next_State <= ST1;
drugo
Next_State <= ST2;
end if;
KADA ST2 => nWait <= '1 ';
Next_State <= ST3;
KADA ST3 => if (nDataStrobe = '0 ') onda
Next_State <= ST3;
drugo
Next_State <= ST4;
end if;
KADA ST4 => if (nWri = '0 ')
Next_State <= ST4;
drugo
Next_State <= ST5;
end if;
KADA ST5 => nWait <= 1;
Next_State <= st0;
Kada drugi => Next_State <= st0;
end case;
Kraj Napredak;PROCES (SysClk)
BEGIN
IF Rising_Edge (SysClk) ONDA
Cur_State <= Next_State;
END IF;
Kraj Napredak;
Akcija END;

 

[cube007]

Pozdrav lzh08,

1.Postoje dva signala nestalo u entitetu: SysClk, Reset.Ako želite sintetizirati koda vam je potrebno resetirati signal za započeti automat:

ŠifraROCES (reset_n, SysClk)

BEGIN

IF reset_n = 0 tada

Cur_State <= st0;

ELSIF Rising_Edge (SysClk) ONDA

Cur_State <= Next_State;

END IF;

Kraj Napredak;