verilog kod za 2. reda IIR pojasni filtar

[newton2006]

Bok,
Nisam upoznat s verilog broj, a sada je potrebno za mene to napisati kod za 2. reda IIR pojasni filtar.8-bit digital signal input za 2. reda IIR pojasni filtar.JA će stvarno poštovati bilo koju vrstu pomoći.

Hvala vam na vašem vremenu.

 

[rsrinivas]

Bok
u nisu dale iskorijeni vrijednosti
međutim, ovdje je 16 bit input 16 bit output 2'nd bi IIR Butterworth BPF.
lfc 250 Hz i HFC 555Hz.
Matlab generirani kod.

/ / Discrete-Time IIR filtra (real)
/ / -------------------------------
/ / Filter Struktura: Direct-Obrazac I, Second-Order Profili
/ / Broj Sections: 1
/ / Stabilan: Da
/ / Linearna faza: Ne
/ / Aritmetički: fiksni
/ / Numerator: s16, 14 -> [-2 2)
/ / Nazivnik: s16, 14 -> [-2 2)
/ / Values Scale: s16, 14 -> [-2 2)
/ / Ulaz: s16, 15 -> [-1 1)
/ / Izlaz: s16, 11 -> [-16 16)
/ / Numerator Država: s16, 15 -> [-1 1)
/ / Nazivnik Država: s16, 15 -> [-1 1)
/ / Numerator Prod: s32, 29 -> [-4 4)
/ / Nazivnik Prod: s32, 29 -> [-4 4)
/ / Numerator Accum: S34, 29 -> [-16 16)
/ / Nazivnik Accum: S34, 29 -> [-16 16)
/ / Okrugli Mode: okrugli
/ / Overflow Mode: zamotati
/ / ------------------------------------------------ -------------

`rokove 1 ns / 1 ns

modul filtar (CLK, clk_enable, reset, filter_in, filter_out);

CLK ulaz;
ulaz clk_enable;
reset ulaz;
input potpisan [15:0] filter_in; / / sfix16_En15
izlaz potpisan [15:0] filter_out; / / sfix16_En11

/ / Local Funkcije
/ / Tip Definicije
/ / Konstante
parametar potpisan [15:0] scaleconst1 = 16'b0000000101011100; / / sfix16_En14
parametar potpisan [15:0] coeff_b1_section1 = 16'b0100000000000000; / / sfix16_En14
parametar potpisan [15:0] coeff_b2_section1 = 16'b0000000000000000; / / sfix16_En14
parametar potpisan [15:0] coeff_b3_section1 = 16'b1100000000000000; / / sfix16_En14
parametar potpisan [15:0] coeff_a2_section1 = 16'b1000001011100110; / / sfix16_En14
parametar potpisan [15:0] coeff_a3_section1 = 16'b0011110101000111; / / sfix16_En14
/ / Signali
žica potpisan [15:0] input_typeconvert; / / sfix16_En15
žica potpisan [15:0] scale1; / / sfix16_En15
žica potpisan [31:0] mul_temp; / / sfix32_En29
/ / Section 1 signali
žica potpisan [33:0] a1sum1; / / sfix34_En29
žica potpisan [33:0] a2sum1; / / sfix34_En29
žica potpisan [33:0] b1sum1; / / sfix34_En29
žica potpisan [33:0] b2sum1; / / sfix34_En29
žica potpisan [15:0] numtypeconvert1; / / sfix16_En15
žica potpisan [15:0] dentypeconvert1; / / sfix16_En15
reg potpisan [15:0] numdelay_section1 [0:1]; / / sfix16_En15
reg potpisan [15:0] dendelay_section1 [0:1]; / / sfix16_En15
žica potpisan [31:0] a2mul1; / / sfix32_En29
žica potpisan [31:0] a3mul1; / / sfix32_En29
žica potpisan [31:0] b1mul1; / / sfix32_En29
žica potpisan [31:0] b3mul1; / / sfix32_En29
žica potpisan [16:0] unaryminus_temp; / / sfix17_En15
žica potpisan [33:0] b1multypeconvert1; / / sfix34_En29
žica potpisan [33:0] add_cast; / / sfix34_En29
žica potpisan [33:0] add_cast_1; / / sfix34_En29
žica potpisan [34:0] add_temp; / / sfix35_En29
žica potpisan [33:0] sub_cast; / / sfix34_En29
žica potpisan [33:0] sub_cast_1; / / sfix34_En29
žica potpisan [34:0] sub_temp; / / sfix35_En29
žica potpisan [33:0] sub_cast_2; / / sfix34_En29
žica potpisan [33:0] sub_cast_3; / / sfix34_En29
žica potpisan [34:0] sub_temp_1; / / sfix35_En29
žica potpisan [15:0] output_typeconvert; / / sfix16_En11

/ / Blok izvještaji
dodijeliti input_typeconvert = filter_in;

dodijeliti mul_temp = input_typeconvert * scaleconst1;
dodijeliti scale1 = (mul_temp [29:13] 1)>>> 1;

/ / ------------------ ------------------ Odjeljak 1

dodijeliti numtypeconvert1 = scale1;

dodijeliti dentypeconvert1 = (a1sum1 [29:13] 1)>>> 1;

Uvijek @ (posedge CLK ili posedge reset)
begin: numdelay_process_section1
if (reset == 1'b1) počinju
numdelay_section1 [0] <= 0;
numdelay_section1 [1] <= 0;
kraj
else begin
if (clk_enable == 1'b1) počinju
numdelay_section1 [0] <= numtypeconvert1;
numdelay_section1 [1] <= numdelay_section1 [0];
kraj
kraj
kraj / / numdelay_process_section1

Uvijek @ (posedge CLK ili posedge reset)
begin: dendelay_process_section1
if (reset == 1'b1) počinju
dendelay_section1 [0] <= 0;
dendelay_section1 [1] <= 0;
kraj
else begin
if (clk_enable == 1'b1) počinju
dendelay_section1 [0] <= dentypeconvert1;
dendelay_section1 [1] <= dendelay_section1 [0];
kraj
kraj
kraj / / dendelay_process_section1

dodijeliti a2mul1 = dendelay_section1 [0] * coeff_a2_section1;

dodijeliti a3mul1 = dendelay_section1 [1] * coeff_a3_section1;

dodijeliti b1mul1 = $ potpisan ((numtypeconvert1 [15:0], 14'b00000000000000));

dodijeliti unaryminus_temp = (numdelay_section1 [1] == 16'b1000000000000000)?$ potpisan ((1'b0, numdelay_section1 [1])):-numdelay_section1 [1];
dodijeliti b3mul1 = $ potpisan ((unaryminus_temp [16:0], 14'b00000000000000));

dodijeliti b1multypeconvert1 = $ potpisan (((2 (b1mul1 [31])), b1mul1));

dodijeliti b1sum1 = b1multypeconvert1;

dodijeliti add_cast = b1sum1;
dodijeliti add_cast_1 = $ potpisan (((2 (b3mul1 [31])), b3mul1));
dodijeliti add_temp = add_cast add_cast_1;
dodijeliti b2sum1 = add_temp [33:0];

dodijeliti sub_cast = b2sum1;
dodijeliti sub_cast_1 = $ potpisan (((2 (a2mul1 [31])), a2mul1));
dodijeliti sub_temp = sub_cast - sub_cast_1;
dodijeliti a2sum1 = sub_temp [33:0];

dodijeliti sub_cast_2 = a2sum1;
dodijeliti sub_cast_3 = $ potpisan (((2 (a3mul1 [31])), a3mul1));
dodijeliti sub_temp_1 = sub_cast_2 - sub_cast_3;
dodijeliti a1sum1 = sub_temp_1 [33:0];

dodijeliti output_typeconvert = (((4 (dentypeconvert1 [15])), dentypeconvert1 [15:3]) 1)>>> 1;

/ / Dodjela izvještaji
dodijeliti filter_out = output_typeconvert;

endmodule / / filterSrinivas