ugoditi pomoć mene! Thx

[lzh08]

sljedeće je izvor code.I misliti count mora biti 8,16 ...... na
St8_1, ali je rezultat simulacije 16,32 ......, zašto?
(korištenje modelsim simulacija)
library IEEE;
korištenje IEEE.Std_Logic_1164.all;
korištenje IEEE.Std_Logic_Unsigned.all;
korištenje IEEE.Std_Logic_Arith.all;

entitet teststate je
luka
(
SysClk: u Std_Logic; - brojač
Reset: in std_logic
);
kraj teststate;

arhitektura Akcija teststate je

tip je State_1 (St0_1, St1_1, St2_1, St3_1, St4_1, St5_1, St6_1, St7_1, St8_1);
signala Cur_State_1, Next_State_1: State_1: = St0_1;
signala count: integer range 0 - 128;

započeti

proces (SysClk Reset)
započeti
ako Reset = '0 'then
count <= 0;
elsif rising_edge (SysClk) tada
slučaj Cur_State_1 je
kad St0_1 => Next_State_1 <= St1_1;
count <= count 1;
kad St1_1 => Next_State_1 <= St2_1;
count <= count 1;
kad St2_1 => Next_State_1 <= St3_1;
count <= count 1;
kad St3_1 => Next_State_1 <= St4_1;
count <= count 1;
kad St4_1 => Next_State_1 <= St5_1;
count <= count 1;
kad St5_1 => Next_State_1 <= St6_1;
count <= count 1;
kad St6_1 => Next_State_1 <= St7_1;
count <= count 1;
kad St7_1 => Next_State_1 <= St8_1;
count <= count 1;
kad St8_1 => Next_State_1 <= St0_1;
count <= count 1;
kada drugi => Next_State_1 <= St0_1;
end case;
end if;
end process;

proces (Reset, SysClk)
započeti
ako Reset = '0 'then
Cur_State_1 <= St0_1;
elsif rising_edge (SysClk) tada
Cur_State_1 <= Next_State_1;
end if;
end process;

Akcija end;

 

[nand_gates]

Provjerite sa sljedećim kod!

Šifra:

library IEEE;

korištenje IEEE.Std_Logic_1164.all;

korištenje IEEE.Std_Logic_Unsigned.all;

korištenje IEEE.Std_Logic_Arith.all;entitet teststate je

luka

(

SysClk: in std_logic; - brojač

Reset: in std_logic

);

kraj teststate;arhitektura Akcija teststate jetip je State_1 (St0_1, St1_1, St2_1, St3_1, St4_1, St5_1, St6_1, St7_1, St8_1);

signala Cur_State_1, Next_State_1: State_1: = St0_1;

signala count: integer range 0 - 128;

signala count_nx: integer range 0 - 128;

započetiproces (Cur_State_1, count)

započeti

slučaj Cur_State_1 je

kad St0_1 => Next_State_1 <= St1_1;

count_nx <= count 1;

kad St1_1 => Next_State_1 <= St2_1;

count_nx <= count 1;

kad St2_1 => Next_State_1 <= St3_1;

count_nx <= count 1;

kad St3_1 => Next_State_1 <= St4_1;

count_nx <= count 1;

kad St4_1 => Next_State_1 <= St5_1;

count_nx <= count 1;

kad St5_1 => Next_State_1 <= St6_1;

count_nx <= count 1;

kad St6_1 => Next_State_1 <= St7_1;

count_nx <= count 1;

kad St7_1 => Next_State_1 <= St8_1;

count_nx <= count 1;

kad St8_1 => Next_State_1 <= St0_1;

count_nx <= count 1;

kada drugi => Next_State_1 <= St0_1;

count_nx <= count;

end case;

end process;proces (Reset, SysClk)

započeti

ako Reset = '0 'then

Cur_State_1 <= St0_1;

count <= 0;

elsif rising_edge (SysClk) tada

Cur_State_1 <= Next_State_1;

count <= count_nx;

end if;

end process;Akcija end;