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manasiw2
Guest
Bok. Trebam učiniti sljedeće, izlaz treba follw ulaza nakon dva ciklusa sustava sat. Molimo sugeriraju kako to učiniti u VHDL. hvala unaprijed.
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L
laststep
Guest
Jednostavan način samo dodati 2 registar po serijala i uzorak izlaz zadnjeg registar.
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mukesh1981
Guest
hi Dovoljno je koristiti dvostruku flopping ništa, ali dvije japanke u seriji, da je izlaz će biti dva sat ciklusi odgođen s obzirom na ulazu.
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manasiw2
Guest
ya sam ga dobio .... hvala svima.