R
roger
Guest
ako koristite verilog, imamo
top.module1.module2.signal
ali ako se koristi mješoviti HDL
kako to ekstrakt signale unutar
<img src="http://www.edaboard.com/images/smiles/icon_cry.gif" alt="Crying or Very sad" border="0" />
top.module1.module2.signal
ali ako se koristi mješoviti HDL
kako to ekstrakt signale unutar
<img src="http://www.edaboard.com/images/smiles/icon_cry.gif" alt="Crying or Very sad" border="0" />